An EU Horizon 2020 Project

Architecting More Than Moore

Wireless Plasticity for Massive Heterogeneous Computer Architectures

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S. Abadal et al., “Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors,” arXiv preprint, arXiv:2011.04107, 2020

L. Duch et al., “Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, 2122 - 2133, 2020.

A. Elnaqib et al., “A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2020.

W.A. Simon et al., “An in-Cache Computing Architecture for Edge Devices,” IEEE Transactions on Computers, 2020.

A. Levisse et al., “Write Termination circuits for RRAM: An Holistic Approach From Technology to Application Considerations,” IEEE Access 8, 109297–109308, 2020.

X. Timoneda et al., “Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication,” IEEE Transactions on Communications 68(5), 3247–3258, 2020.

S. Abadal et al., “Wave Propagation and Channel Modeling in Chip-Scale Wireless Communications: A Survey from Millimeter-Wave to Terahertz and Optics,” IEEE Access 8, 278–293, 2019.

Conference Publications

A. Franques et al., “WiDir: A Wireless-Enabled Directory Cache Coherence Protocol,” in Proc. HPCA-27, Seoul, South Korea, February 2021.

A. Franques et al., “Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Many-Core CMPs,” in Proc. DATE 2021, Grenoble, France, February 2021.

R. Guirado et al., “Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package,” in Proc. ASP-DAC '21, Tokyo, Japan, January 2021.

M. Imani et al., “Toward Dynamically Adapting Wireless Intra-Chip Channels to Traffic Needs with a Programmable Metasurface,” ACM International Workshop on Nanoscale Computing, Communication, and Applications (NanoCoCoA), virtual, November 2020.

H. Okuhara et al., “An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain, pp. 1-5, 2020.

G. Ottavi et al., “Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference,” in Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, pp. 512-517, 2020.

W. A. Simon et al., “A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance,” in Proc. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Salt Lake City, Utah, USA, 2020.

N. Bruschi et al., “Enabling mixed-precision quantized neural networks in extreme-edge devices,” in Proc. 17th ACM International Conference on Computing Frontiers (CF ’20). Association for Computing Machinery, New York, NY, USA, pp. 217–220, 2020.

A. Levisse et al., “Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems,” in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Barcelona, Spain, 2020, pp. 1549–1552.

H. Najibi et al., “Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology,” in Proc. ACM Great Lakes Symposium on VLSI (GLSVLSI), Beijing, China, 2020.

H. Najibi et al., “Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoC with On-Chip Switched Capacitor Converters,” in Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020. (Best Paper Award)

R. Guirado et al., “Understanding the Impact of On-Chip Communication on DNN Accelerator Performance,” in Proc. ICECS ’19, Genova, Italy, November 2019.

Invited Talks, Lectures & Panels

Zhenxing Wang, “Metal-Insulator-Graphene RF Diodes: From Devices to Integrated Circuits,” Joint Spring MOS-AK Workshop and Symposium on Schottky Barrier MOS (SB-MOS) devices with IEEE EDS Mini-Colloquium on „Non-conventional Devices and Technologies“, October 2020.

Sergi Abadal and Filip Lemic, “Terahertz Nanocommunication and Networking: Emerging Applications, Approaches, and Open Challenges,” ACM International Conference on Nanoscale Computing and Communication (NANOCOM), September 2020.

A. Sebastian et al., “Unconventional computing and what it means for the future of interconnects,” International Workshop on Network on Chip Architectures (NoCArc), held within the IEEE/ACM International Symposium on Microarchitecture, October 2020.

A. Levisse et al., “Demonstrating In-Cache Computing Thanks to Cross-Layer Design Methodologies,” Design Automation and Test in Europe (DATE), Special Session on In-Memory Computing for Edge AI, Grenoble (FR), Virtual Event April 2020.

A. Levisse et al., “Rendre efficace l’intelligence artificielle dans l’Edge grâce aux technologies et architectures mémoires émergentes,” Francophone winter school on design techniques for embedded systems design (Ecole d’Hiver francophone sur la technologie de conception des systèmes embarqués hétérogènes – FETCH), Montréal, Canada, Feb. 2020.

Workshops & Tutorials

M. Zapater et al., Tutorial: “Using gem5 and full- system RISC-V simulation to enable the optimization of heterogeneous architectures,” High Performance and Embedded Architecture and Compilation (HiPEAC), January 2021.

EU logo This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 863337.

Project Coordination: Sergi Abadal (UPC)