Selected Publications
S. Abadal et al., “Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors,”
IEEE Wireless Communications Magazine, 2022.
This position paper, with contributions of all the project partners, provides an overview of the vision of the WiPLASH project and the challenges that could be found along the way from the electronics, electromagnetics, and computer architecture perspectives.
M. Elsayed, R. Negra, “
Graphene-Based Microwave Circuits: A Review,”
Advanced Materials, 2022.
This paper gives an overview of the microwave integrated circuits based on graphene, including the AMO/RWTH in-house developed MMIC process, utilized for the graphene transceiver in WiPLASH.
T. Knobloch et al., “Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning,” Nature Electronics, 2022.
This paper proposes a novel way to improve the stability of transistors based on 2D materials, namely tuning the Fermi-level of 2D materials away from the defects band in the gate oxide. It guides us to use 2D materials in a smart way, which is crucial in the WiPLASH project.
A. Hemmetter et al., “Terahertz Rectennas on Flexible Substrates Based on One-Dimensional Metal–Insulator–Graphene Diodes,”
ACS Appl. Electron. Mater, 2021.
This paper demonstrates a flexible THz rectenna based on graphene, in which metal-insulator-graphene diode is used as a rectifier connected to metal antenna, with the application in energy harvesting.
F. Rodríguez-Galán et al., “Towards Spatial Multiplexing in Wireless Networks within Computing Packages,”
Proc. ACM NANOCOM’22, Barcelona, Spain, October 2022.
This work delivers insight about the possible existence of multiple spatial channels within a flip-chip computing package using an antenna array to steer/concentrate the electric field over certain regions of the chip.
A. Franques et al.,
“Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Many-Core CMPs,”
Proc. DATE 2021, Grenoble, France, February 2021.
This work presents and evaluates a Medium Access Control (MAC) protocol that, with very simple rules, aims to deliver the low latency of random access protocols and the high throughput of token passing.
A. Garofalo et al., “A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks,”
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2022.
The paper presents a heterogeneous tightly-coupled clustered architecture integrating 8 RISC-V cores, an in-memory computing accelerator (IMA), and digital accelerators. It explores the requirements for end-to-end inference of a full mobile-grade DNN (MobileNetV2) in terms of IMC array resources, by scaling up our heterogeneous architecture to a multi-array accelerator. The results show that the proposed solution, on the end-to-end inference of the MobileNetV2, is one order of magnitude better in terms of execution latency than existing programmable architectures and two orders of magnitude better than state-of-the-art heterogeneous solutions integrating in-memory computing analog cores.
N. Bruschi et al., “End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture,”
Proc. DATE 2023, Antwerp, Belgium, April 2023.
The paper presents the full inference of an end-to-end ResNet-18 DNN on a 512-cluster heterogeneous architecture coupling a mix of AIMC cores and digital RISC-V cores, achieving up to 20.2 TOPS. It analyzes the mapping of the network on the available non-volatile cells, compares it with state-of-the-art models, and derives guidelines for next-generation many-core architectures based on AIMC devices.
J. Klein et al., “ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning,”
IEEE Transactions on Computers. 2022.
The paper illustrates a novel system architecture that tightly integrates analog in-memory computing accelerators into multi-core CPUs systems. It introduces a gem5-X-based full system-level simulation framework, ALPINE, which enables an in-depth characterization of the proposed architecture.
R. Medina et al., “System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms,”
Proc. ASP-DAC 2023, Tokyo, Japan, January 2023.
The paper presents an exploration of the performance of in-package wireless communication from a system perspective, based on dedicated extensions to the gem5-X simulator. We consider different Medium Access Control (MAC) protocols, as well as applications with different runtime profiles, showcasing that current in-package wireless solutions are competitive with wired chiplet interconnects.
N. Bruschi et al., “Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference,”
Proc. AICAS 2022, Incheon, Korea, June 2022.
This work presents a many-tile AIMC architecture with inter-tile wireless communication that integrates multiple heterogeneous computing clusters, embedding a mix of parallel RISC-V cores and AIMC tiles. It performs an extensive design space exploration of the proposed architecture and discusses the benefits of exploiting emerging on-chip communication technologies such as wireless transceivers in the millimeter-wave and terahertz bands.
R. Guirado et al.,
“Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package,”
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, January 2021.
This work performs an early-stage exploration of the possible architectures and dataflows that could be employed for scaling DNN accelerators over multiple chiplets, while accounting for the inherent broadcast capabilities of wireless communications.
Journals
F. Conti et al., “Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing,,” IEEE Journal of Solid-State Circuits. 2023
M Ríos, et al., “Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference,,” IEEE Transactions on Emerging Topics in Computing. 2023
F. Ponzina et al., “Overflow-free compute memories for edge AI acceleration,” ACM Transactions on Embedded Computing Systems. 2023
V. Pecunia et al., “Roadmap on energy harvesting materials.,” J. Phys. Mater., 6, 042501. 2023
R. Guirado, et al., “WHYPE: A Scale-Out Architecture with Wireless Over-the-Air Majority for Scalable In-memory Hyperdimensional Computing,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2023
P. Palacios et al., “Design Considerations for a Low-Power Fully Integrated MMIC Parametric Upconverter in SiGe BiCMOS,” IEEE Journal of Solid-State Circuits. 2023
G. Ottavi et al., “Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode,” IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
J. Klein et al., “ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning,” IEEE Transactions on Computers. 2022
F. Ponzina et al., “Using Algorithmic Transformations and Sensitivity Analysis to Unleash Approximations in CNNs at the Edge,” MDPI Micromachines, 2022
S. Abadal et al., “ Computing Graph Neural Networks: A Survey from Algorithms to Accelerators ,” ACM Computing Surveys, 2022
M. Elsayed, R. Negra, “ Graphene-Based Microwave Circuits: A Review,” Advanced Materials, 2022
E. Reato, R. Negra, “Zero Bias Power Detector Circuits based on MoS 2 Field Effect Transistors on Wafer‐Scale Flexible Substrates,” Advanced Materials, 2022
N.Halima, “Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters.,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022
M. Lemme et al., “2D materials for future heterogeneous electronics,” Nature Communications, 2022
F. Ponzina et al., “A hardware/software co-design vision for deep learning at the edge,” IEEE Micro, 2022
A. Garofalo et al., “A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2022
A. Garofalo et al., “Darkside: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training,” IEEE Open Journal of the Solid-State Circuits Society, 2022
S. Abadal et al., “Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors,” IEEE Wireless Communications Magazine, 2022
T. Knobloch et al. “Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning,” Nature Electronics, 2022
A. Ganguly et al. “Interconnects for DNA, Quantum, In-Memory and Optical Computing: Insights from a Panel Discussion,” IEEE Micro, 2022
D. Rossi et al., “Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode,” IEEE Journal of Solid-State Circuits, 2021
A. Hemmetter et al., “Terahertz Rectennas on Flexible Substrates Based on One-Dimensional Metal–Insulator–Graphene Diodes,” ACS Appl. Electron. Mater, 2021
H. Okuhara et al., “A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021
F. Montagna et al., “A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics,” IEEE Transactions on Parallel and Distributed Systems, 2021
M. Imani et al. “Metasurface-Programmable Wireless Network-on-Chip,” Advanced Science, 2021
F. Lemic et al. “Survey on Terahertz Nanocommunication and Networking: A Top-Down Perspective,” IEEE Journal on Selected Areas in Communications, 36(9), 1506-1543, 2021
K. Rouhi et al. “Multi-Channel Near-Field Terahertz Communications Using Reprogrammable Graphene-Based Digital Metasurface,” IEEE/OSA Journal of Lightwave Technology, 2021
Y. M. Qureshi et al. “Gem5-X: A Many-Core Heterogeneous Simulation Platform for Architectural Exploration and Optimization,” ACM Transactions on Architecture and Code Optimization (TACO), 2021
F. Ponzina et al. “E2CNN: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices,” IEEE Transactions on Computers, 2021
C.-Y. Fan et al. “Fully Integrated 2.4-GHz Flexible Rectifier Using Chemical-Vapor-Deposition Graphene MMIC Process,” IEEE Transactions on Electron Devices, 68 (1326), 2021
M. Saeed et al. “Voltage-Tunable Thin Film Graphene-diode-based Microwave Harmonic Generator,” IEEE Microwave and Wireless Components Letters, 2021
Z. Wang et al. “Graphene in 2D/3D Heterostructure Diodes for High Performance Electronics and Optoelectronics ,” Adv. Electron. Mat., 2021
F. Glaser et al. “Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters,” IEEE Transactions on Parallel and Distributed Systems, 32(3), 633-648, 2021
A. Garofalo et al. “XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes ,” IEEE Transactions on Emerging Topics in Computing, 2021
A. Burrello et al. “DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs,” IEEE Transactions on Computers, 2021
L. Duch et al., “Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, 2122 - 2133, 2020.
Y.Qurechi et al., “Genome sequence alignment-design space exploration for optimal performance and energy architectures.,” IEEE Transactions on Computers, 2020
A. Elnaqib et al., “A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2020.
W.A. Simon et al., “An in-Cache Computing Architecture for Edge Devices,” IEEE Transactions on Computers, 2020.
A. Levisse et al., “Write Termination circuits for RRAM: An Holistic Approach From Technology to Application Considerations,” IEEE Access 8, 109297–109308, 2020.
X. Timoneda et al., “Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication,” IEEE Transactions on Communications 68(5), 3247–3258, 2020.
S. Abadal et al., “Wave Propagation and Channel Modeling in Chip-Scale Wireless Communications: A Survey from Millimeter-Wave to Terahertz and Optics,” IEEE Access 8, 278–293, 2019.
Conference Publications
F. Rodríguez-Galán, et al., “Collective Communication Patterns using Time-Reversal Terahertz Links at the Chip Scale,” Proceedings of the IEEE GLOBECOM ‘23, Kuala Lumpur, Malaysia, December 2023.
R. Medina Morillas, et al., “REMOTE: Re-thinking Task Mapping on Wireless 2.5 D Systems-on-Package for Hotspot Removal,” Proceedings of VLSI-SoC, Dubai, United Arab Emirates, October 2023.
A. Bandara, et al., “Exploration of Time Reversal for Wireless Communications within Computing Packages,” Proceedings of the ACM NANOCOM’23, Coventry, UK, September 2023.
E. Pereira de Santana, et al., “Tunable Plasmonic Graphene Antenna Array for Communications at THz Frequencies,” Proceedings of IRMMW-THz, Montreal, Canada, September 2023.
K. Pathak, et al., “Validating Full-System RISC-V Simulator: A Systematic Approach,” RISC-V Summit Europe, Barcelona, Spain, June 2023.
B. Ollé, et al., “Multi-Channel Medium Access Control Protocols for Wireless Networks Within Computing Packages,” Proceedings of the IEEE ISCAS 2023, Monterey, USA, May 2023.
N. Bruschi et al., “End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture,” In Proc. DATE 2023, Antwerp, Belgium, April 2023.
A. Amirshahi et al., “TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers,” in Proc. ASP-DAC 2023, Tokyo, Japan, January 2023.
R. Medina et al., “System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms,” in Proc. ASP-DAC 2023, Tokyo, Japan, January 2023.
F. Ponzina et al., “An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs.,” International Conference on Omni-layer Intelligent Systems (COINS), 2022
R. Medina et al., “Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures.,” Latin America Symposium on Circuits and System (LASCAS), 2022
F. Rodríguez-Galán et al., “Towards Spatial Multiplexing in Wireless Networks within Computing Packages,” in Proc. ACM NANOCOM’22, Barcelona, Spain, October 2022.
E. Pereira de Santana, et al.,“Integrated Graphene Patch Antenna For Communications At THz Frequencies,” in Proc. IRMMW-THz, Delft, The Netherlands, September 2022.
R. Guirado et al., “Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing,” in Pro. IJCNN/WCCI 2022, Padova, Italy, July 2022.
N. Bruschi et al., “Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference,” in Proc. AICAS 2022, Incheon, Korea, June 2022
M. Rios et al., “Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge.,” Great Lakes Symposium on VLSI, 2022
Y. Tortorella et al., “ RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs ,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022
N. Halima et al., “Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays.,” Great Lakes Symposium on VLSI, 2022
N. Bruschi et al., “GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors,” IEEE 39th International Conference on Computer Design (ICCD), 2021
M. Elsayed, R. Negra, “Low-cost Compact Analogue Phase-Shifter based on CVD Graphene-diode for Smart Surfaces Applications,” IMS, 2021
M. Elsayed, R. Negra, “Compact V-Band MMIC Square-law Power Detector with 70 dB Dynamic Range exploiting State-of-the-art Graphene diodes,” IMS, 2021
R. Guirado et al., “ Characterizing the Communication Requirements of GNN Accelerators: A Model-Based Approach ,” IEEE International Symposium on Circuits and Systems (ISCAS), 2021
R. Guirado et al., “Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package,” in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, January 2021.
M. A. Rios et al., “Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing,” in Proc. Design, Automation and Test in Europe Conference (DATE), Virtual Conference and Exhibition, February 1-5, 2021
G. Ottavi et al., “End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet?” in Proc. IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021.
J. Klein et al., “Architecting More Than Moore - Wireless Plasticity for Massive Heterogeneous Computer Architectures (WiPLASH)” in Proc. ACM International Conference on Computing Frontiers (CF), 2021.
A. Franques et al., “WiDir: A Wireless-Enabled Directory Cache Coherence Protocol,” in Proc. HPCA-27, Seoul, South Korea, February 2021.
A. Franques et al., “Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Many-Core CMPs,” in Proc. DATE 2021, Grenoble, France, February 2021.
W. A. Simon et al., “A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance,” in Proc. IFIP/IEEE International Conference on Very Large Scale Integration, 2020.
M. Imani et al., “Toward Dynamically Adapting Wireless Intra-Chip Channels to Traffic Needs with a Programmable Metasurface,” ACM International Workshop on Nanoscale Computing, Communication, and Applications (NanoCoCoA), virtual, November 2020.
H. Okuhara et al., “An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain, pp. 1-5, 2020.
G. Ottavi et al., “Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference,” in Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, pp. 512-517, 2020.
N. Bruschi et al., “Enabling mixed-precision quantized neural networks in extreme-edge devices,” in Proc. 17th ACM International Conference on Computing Frontiers (CF ’20). Association for Computing Machinery, New York, NY, USA, pp. 217–220, 2020.
A. Levisse et al., “Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems,” in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Barcelona, Spain, 2020, pp. 1549–1552.
H. Najibi et al., “Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology,” in Proc. ACM Great Lakes Symposium on VLSI (GLSVLSI), Beijing, China, 2020.
H. Najibi et al., “Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoC with On-Chip Switched Capacitor Converters,” in Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020. (Best Paper Award)
R. Guirado et al., “Understanding the Impact of On-Chip Communication on DNN Accelerator Performance,” in Proc. ICECS ’19, Genova, Italy, November 2019.
This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 863337.
Project Coordination: Sergi Abadal (UPC)
www.upc.edu